1. Field of the Invention
The present invention relates to a method of manufacturing a semiconductor device which is characterized by a stacking structure of a semiconductor element (chip).
2. Description of the Related Art
With decreases in the size of electronic devices in recent years, when semiconductor devices are packaged, various methods are used which make it possible to package the semiconductor devices at a high integration density. A semiconductor device called a wafer level chip size package (Wafer-level Chip-Package: be to referred to as W-CSP hereinafter)is known. It his a package size that is almost equal to that of a bare chip, or slightly larger than a bare chip.
A feature of the W-CSP will be described below.
A second semiconductor element having a size smaller than that of a first semiconductor element is stacked on the first semiconductor element. On the surfaces of the first and second semiconductor elements, an electronic circuit constituted by a transistor, a resistor, a capacitor, an inductor, and the like is formed. On the surface of the first semiconductor element, a plurality of electrode pads connected to the electronic circuit is formed. On the surface of the second semiconductor element, a plurality of electrodes connected to the electronic circuit is formed. The electrode pads formed on the first semiconductor element are electrically connected to the electrodes formed on the second semiconductor element to transmit electric signals.
A method of manufacturing the W-CSP will be described below.
A wafer which is diced into independent first semiconductor elements in the subsequent steps is prepared. An electric circuit for constituting the first semiconductor elements is formed on the surface of the wafer. Respective second semiconductor elements are placed on the wafer. At this time, electrodes formed on the second semiconductor elements are electrically connected to the electronic circuit formed on the surface of the wafer. Thereafter, the wafer and all the second semiconductor elements are sealed by a sealing resin, and then diced into independent semiconductor devices.
However, in the manufacturing method, the respective second semiconductor elements must be aligned to the wafer, so that the steps are complicated. In addition, since the wafer and the sealing resin are different in thermal contraction, the wafer may warp by the influence of thermal contraction of the sealing resin, disadvantageously.